The present invention relates, in general, to the field of integrated circuit devices incorporating memory arrays. More particularly, the present invention is related to a small signal, low power xe2x80x9creadxe2x80x9d data bus driver for integrated circuit memory devices incorporating dynamic random access memory (xe2x80x9cDRAMxe2x80x9d) arrays.
Integrated circuit DRAM chips are large, rectangular arrays of memory cells with support logic used for reading and writing data into the arrays, and refresh circuitry used to maintain the integrity of the stored data. Memory arrays are arranged in rows and columns of memory cells connected to word lines and bit lines. Each memory cell has a unique location or address defined by the intersection of a row line and a bit line.
A single DRAM memory cell is typically a capacitor and pass transistor wherein the capacitor is charged to produce a logic one or discharged to produce a logic zero. An integrated circuit memory chip includes support circuitry that allows the user to read the data stored in the memory""s cells, write to the memory cells, and refresh the memory cells. This supporting circuitry generally includes sense amplifiers that are used to amplify the signal or charge detected in a memory cell, address logic to select specific rows and columns of memory, row address select and column address select logic used to latch and resolve the row and column addresses and to initiate and terminate read and write operations, read and write circuitry to store information in the memory""s cells or to read stored data, internal counters or registers to keep track of the refresh sequence, or to initiate refresh cycles as need, and output enable logic used to prevent data from appearing at the outputs unless specifically desired.
The xe2x80x9cread data pathxe2x80x9d circuitry of a DRAM chip typically includes global read data lines, a read amplifier, and a sense amplifier coupled to the bit lines. In prior art read data paths the global read data lines are coupled directly to the read amplifier. The read data lines must typically be pre-charged and have a voltage swing between ground or VSS and the full VCC power level. This manner of operation wastes power or, alternatively, reduces data line switching speed for a given power rating.
What is desired, therefore, is read path circuitry for an integrated circuit DRAM in which pre-charging of the read data lines is not necessary, power is reduced, and read data line switching speed is improved.
Disclosed herein is a small signal, low power xe2x80x9creadxe2x80x9d data bus driver for integrated circuit devices incorporating memory arrays which serves to reduce power requirements by not precharging the read data lines and by reducing the voltage swing on the read data lines. In a representative embodiment, a push-pull driver stage in a local read data driver (xe2x80x9cLRDDxe2x80x9d) is used between the complementary local read data lines (xe2x80x9cDRLxe2x80x9d, xe2x80x9cDRLBxe2x80x9d) and the global read data lines (xe2x80x9cDRxe2x80x9d, xe2x80x9cDRBxe2x80x9d) to eliminate the need to precharge the global read data lines. The LRDD drives the global read data lines between circuit ground (VSS) and a threshold voltage below the supply voltage level (VSS-Vtn) which reduces the voltage swing on these lines. The elimination of the precharge operation and the reduced voltage swing both serve to reduce the power consumption of the device. Advantageously, the LRDD also serves to buffer the memory array read amplifier in the sense amplifier from the global read data lines.